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Chiplet Systems Design/Architecture Engineer

Analog Devices is committed to investing in our people and their growth. One way we can do this is by establishing a cutting-edge Early Career Hiring program. This program features high impact professional development, opportunities to drive meaningful projects that are directly tied to business goals, and unique executive exposure. Our duty is to develop the next generation of talent in our communities and provide them with a pathway to apply their academic skills in the real-world. At ADI, our early career hires will learn from the brightest minds who are dedicated to their growth, development, and success. From an industry perspective, incoming new career hires are surrounded by employees that represent the best of the best minds in their respective fields. Apply now for the opportunity to grow your career and help innovate ahead of what’s possible!

The Advanced Technology Group in the Chief Technology Office is looking for a Systems Architecture Engineer to become a chiplet interface point of contact. You will be part of a larger team that addresses next generation technology needs ranging from process development to circuit design and heterogeneous packaging. This role focused on research and development projects for chiplet-based designs for all of ADI. The broader goal of this position is to drive and align ADI’s die-to-die interface and chiplet architecture and identify future areas of work. This will require a detailed understanding product line needs / roadmaps and taking a higher-level system view to solve problems.

Responsibilities include, but not limited to:

  • Support development efforts to apply standard chiplet interfaces such as BoW, UCIe or XSR to converter and other products
  • Support product lines with die-disaggregation case studies
  • Work with external IP providers on D2D interfaces to adjust technology to our needs
  • Participate in and contribute to chiplets standards organizations like UCIe and ODSA
  • Coordinate internal chiplet research and development projects
  • Liaison for possible chiplet-related research projects (ADI, university, externally funded)
  • Attend chiplet and HI workshops/conferences and disseminate information

Minimum qualifications:

  • M.S. Degree in Electrical Engineering or related discipline, PhD is a plus
  • Typically requires 2-4 years related and progressive experience, more is a plus
  • Exposure to JESD 204c/d standard and other high-speed SERDES
  • Familiarity with networks-on-chip such as AMBA bus, Arteris NOC
  • Experience with system modeling software such as Matlab, Simulink, SystemVue or similar for modeling protocol and synchronization requirements and proposals

Preferred qualifications:

  • Experience with:
    • PCIe, UCIe, JESD204B/C, High-Speed SERDES
    • PLL's and System Level Noise Simulation
    • High-Speed Converters, Performance Requirements and Evaluation
    • Supply Bypass and Decoupling